A team of engineers at the University of Michigan have presented a new chip design that will finally help us break free from the quantum level limitations that undermine our effort to keep up with the Moore’s Law dictations. At this time, semiconductor manufacturing is peaking at 7nm of node fabrication, but experts aren’t very confident that we can squeeze things any further without having to go through some fundamental changes. Simply put, manufacturers need to maintain a certain spacing and pitching between the transistors, otherwise, things will start to behave strangely, and often wrongfully.
Using the “industry-standard” 2D configuration and the most advanced forms of lithography, we have started having trouble catching up with Moore’s Law predictions since the early 2010s. While many started to consider manufacturing costs and energy consumption as explanatory elements for the slowdown, others turned to more radical thinking. Building the chip in a 3D configuration was one of the ideas that gained traction, but things are often a lot more complicated when you have to work with actual chip testing wafers.
The Michigan team has finally managed to designed a 3D chip featuring two layers of transistors in separate arrays. The additional second layer can handle higher voltages, and is made out of an amorphous metal oxide. The first layer is just an “off the shelf” low-voltage integrated circuit. To avoid having trouble with voltage switching, the team decided to use an ohmic contact structure for the top layer. After merging the two layers with heat, zinc, and tin, the team ended up with a very thin and compact chip that has a much higher transistor count. Theoretically, and since each layer is only 75 nanometers thick, the engineers could potentially cramp more layers of transistors, ending up with a chip that will surpass anything that was predicted by Moore’s Law for 2020, or even later.
To learn more about this new method of silicon chip design, check out the complete study.